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cy8c20111, cy8c20121 capsense ? express? ? one button and two button capacitive controllers cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-53516 rev. *h revised may 31, 2012 capsense ? express? ? one button and two button capacitive controllers features capacitive button input tied to a configurable output ? robust sensing algorithm ? high sensitivity, low noise ? immunity to rf and ac noise ? low radiated emc noise ? supports wide range of input capacitance, sensor shapes, and sizes target applications ? printers ? cellular handsets ? lcd monitors ? portable dvd players industry's best configurability ? custom sensor tuning ? output supports strong 20 ma sink current ? output state can be controlled through i 2 c or directly from capsense input state ? run time reconfigurable over i 2 c advanced features ? plug-and-play with factory defa ults ? tuned to support up to 1 mm overlay ? nonvolatile storage of custom settings ? easy integration into existing products ? configure output to match system ? no external components required ? world class free configuration tool wide range of operating voltages ? 2.45 v to 2.9 v ? 3.10 v to 3.6 v ? 4.75 v to 5.25 v i 2 c communication ? supported from 1.8 v ? internal pull-up resistor support option ? data rate up to 400 kbps. ? configurable i 2 c addressing industrial temperature range: ?40 c to +85 c available in 8-pin soic package overview the capsense ? express? controllers support two capacitive sensing (capsense) buttons and two general purpose outputs in cy8c20121 and one capsense button and one general purpose output in cy8c20111. the device functionality is configured through the i 2 c port and can be stored in on-board nonvolatile memory for automat ic loading at power on. the digital outputs are controlled from capsense inputs in factory default settings, but are user configurable for direct control through i 2 c. the four key blocks that make up the cy8c20111 and cy8c20121 controllers are: a r obust capacitive sensing core with high immunity against radiated and conductive noise, control registers with nonvolatile storage, configurable outputs, and i 2 c communications. the user can configure registers with parameters needed to adjust the operation and sensitivity of the capsense buttons and outputs and permanently store the settings. the standard i 2 c serial communication interface allows the host to configure the device and read sensor information in real time. i 2 c address is fully configur able without any external hardware strapping.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 2 of 44 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 pinouts .............................................................................. 4 pin definitions .................................................................. 4 typical circuits ................................................................. 5 operating modes .............................................................. 8 normal mode ............................................................... 8 setup mode ................................................................. 8 i2c interface ...................................................................... 8 i2c device addressing ........ ........................................ 8 i2c clock stretching .................................................... 8 format for register write and read ........................... 9 registers ........................................................................... 9 register conventions .................................................. 9 register map ............................................................. 10 capsense express commands ................................ 11 output_status ................................................... 12 output_port ........................................................ 12 cs_enable ............................................................. 12 dig_enable ............................................................ 13 set_strong_dm .................................................. 13 op_sel_x ................................................................. 15 logical_opr_inputx .......................................... 15 cs_noise_th ......................................................... 16 cs_bl_upd_th ....................................................... 16 cs_setl_time ........................................................ 16 cs_oth_set ........................................................... 17 cs_hysterisis ...................................................... 17 cs_debounce ....................................................... 18 cs_neg_noise_th ................................................ 18 cs_low_bl_rst .................................................... 18 cs_filtering ......................................................... 19 cs_scan_pos_x .................................................... 19 cs_finger_th_x ................................................... 20 cs_idac_x ............................................................... 20 i2c_addr_lock ....... .............. .............. ........... ....... 20 device_id ............................................................... 21 device_status ..................................................... 21 i2c_addr_dm ......... .............. ............... ........... ........ 22 cs_read_button ................................................. 22 cs_read_blx ......................................................... 23 cs_read_diffx ...................................................... 23 cs_read_rawx ..................................................... 23 cs_read_status ................................................. 24 command_reg ...................................................... 24 layout guidelines and best practices ......................... 26 example pcb layout design with two capsense buttons and two leds .................... 28 operating voltages ......................................................... 29 capsense constraints ................................................... 29 absolute maximum ratings .......................................... 30 operating temperature .................................................. 30 electrical specifications ................................................ 31 dc electrical specifications ...................................... 31 capsense electrical characteristics ......................... 33 ac electrical specifications ....................................... 33 appendix ......................................................................... 35 examples of frequently used i2c commands ......... 35 ordering information ...................................................... 36 ordering code definitions ..... .................................... 36 thermal impedances ...................................................... 36 solder reflow specifications ........................................ 36 package diagram ............................................................ 37 acronyms ........................................................................ 38 document conventions ................................................. 38 units of measure ....................................................... 38 numeric conventions ............ .................................... 38 glossary .......................................................................... 39 document history page ................................................. 43 sales, solutions, and legal information ...................... 44 worldwide sales and design s upport ......... .............. 44 products .................................................................... 44 psoc solutions ......................................................... 44
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 3 of 44 pinouts figure 1. 8-pin soic (150 mils) pinout cy8c20111 (1 button) pin definitions 8-pin soic cy8c20111 (1 button) pin no name description 1v ss ground 2i2c scli 2 c clock 3i2c sdai 2 c data 4 cs0 capsense input 5 nc no connect 6 dig0 digital output 7 nc no connect 8v dd supply voltage
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 4 of 44 pinouts figure 2. 8-pin soic (150 mils) pinout cy8c20121 (2 button) pin definitions 8-pin soic cy8c20121 (2 button) pin no name description 1v ss ground 2i2c scli 2 c clock 3i2c sdai 2 c data 4 cs0 capsense input 5 cs1 capsense input 6 dig0 digital output 7 dig1 digital output 8v dd supply voltage
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 5 of 44 typical circuits figure 3. circuit-1: one button and one led [1] figure 4. circuit-2: one button and one led with i 2 c interface ? ? note 1. the sensors are factory tuned to work with 1 mm plastic or glass overlay.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 6 of 44 figure 5. circuit-3: two buttons and two leds with i 2 c interface figure 6. circuit-4: compatibility with 1.8 v i 2 c signaling [2, 3] typical circuits (continued) ? ? note 2. 1.8 v ?? v dd _i2c ?? v dd _ce and 2.4 v ?? v dd _ce ?? 5.25 v. 3. the i2c drive mode of the capsense devic e should be configured properly before using in an i2c environment with external pull -ups. please refer to i2c_addr_dm register and its factory setting.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 7 of 44 figure 7. circuit-5: powering down capsense express device for low power requirements [4] typical circuits (continued) master or host ldo capsense express i2c pull ups led i2c bus sda scl vdd output output enable note 4. for low power requirements, if vdd is to be turned off, the above concept can be used. the vdds of capsense express, i2c pull -ups, and leds must be from the same source. turning off the vdd ensures that no signal is appli ed to the device while it is unpowered. the i2c signals should not be driven high by the master in this situation. if a port pin or group of port pins can cater to the power supply requirement of the circuit, the ldo can be av oided.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 8 of 44 operating modes normal mode in normal mode of operation, the acknowledgment time is optimized. the timings remain approximately the same for different configurations of the slave. to reduce the acknowledgment times in normal mode, the registers 0x07, 0x08, 0x11, 0x50, 0x51, 0x5c, 0x5d are given only read access. writing to these registers can be done only in setup mode. setup mode all registers have read and write access (except those which are read only) in this mode. the acknowledgment times are longer compared to normal mode. when capsense scanning is disabled (command code 0x0a in command register 0xa0), the acknowledgment times can be improved to values similar to the normal mode of operation. i 2 c interface the capsense express devices support the industry standard i 2 c protocol, which can be used to: configure the device read the status and data registers of the device control device operation execute commands the i 2 c address can be modified during configuration. i 2 c device addressing the device uses a seven bit addressing protocol. the i 2 c data transfer is always initiated by the master sending one byte address; first 7-bit contains address and lsb indicates the data transfer direction. zero in the lsb indicates the write transaction form master and one indicates read transfer by the master. ta b l e 3 shows example for different i 2 c addresses. i 2 c clock stretching ?clock stretching? or ?bus stalling? in i 2 c communication protocol is a state in which the slave holds the scl line low to indicate that it is busy. in this conditio n, the master is expected to wait until the scl is released by the slave. when an i 2 c master communicates with the capsense express device, the capsense express stalls the i 2 c bus after the reception of each byte (that is, just before the ack/nak bit) until processing of the byte is complete and critical internal functions are executed. use a fully i 2 c compliant master to communicate with the capsense express device. an i 2 c master which does not support clock stretching (a bit banged software i 2 c master) must wait fo r a specific amount of time specified (as shown in the section format for regi ster write and read ) for each register write and read operation before the next bit is transmitted. it is mandatory to check the scl status (it should be high) before i 2 c master initiates an y data transfer with capsense express. if the master fails to do so and continues to communicate, the communication is erroneous. the following diagrams represent the ack time delays shown in the register map on page 7. figure 8. write ack time representation table 1. i 2 c addresses 7-bit slave address (in dec) d7 d6 d5 d4 d3 d2 d1 d0 8-bit slave address (in hex) 1 00000010(w) 02 1 00000011(r) 03 75 10010110(w) 96 75 10010111(w) 97
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 9 of 44 figure 9. read ack time representation format for register write and read register write format register read format legends registers start slave addr + w a reg addr adata adata a . . . . . data a stop start slave addr + w a reg addr astop start slave addr + r a data a data a . . . . . data nstop master a ? ack slave n ? nak register conventions convention description rw register have both read and write access r register have only read access wpr write register with pass code fd factory defaults
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 10 of 44 register map name register address (in hex) access writable only in setup mode [5] factory default values of registers (in hex) i 2 c max ack time in normal mode (ms) [6] i 2 c max ack time in setup mode (ms) [6] page no. 1 button 2 button output_port 04 w ? 01 03 0.10 ? 12 cs_enable 07 rw yes 01 03 ? 11 12 dig_enable 08 rw yes 01 03 ? 11 13 set_strong_dm 11 rw yes 01 03 ? 11 13 op_sel_0 1c rw ? 82 82 0.12 11 15 logical_opr_input0 1e rw ? 01 01 0.12 11 15 op_sel_1 [7] 21 rw ? 82 0.12 11 15 logical_opr_input1 [7] 23 rw ? 02 0.12 11 15 cs_noise_th 4e rw ? 28 28 0.11 11 16 cs_bl_upd_th 4f rw ? 64 64 0.11 11 16 cs_setl_time 50 rw yes a0 a0 ? 35 16 cs_oth_set 51 rw yes 00 00 ? 35 17 cs_hysterisis 52 rw ? 0a 0a 0.11 11 17 cs_debounce 53 rw ? 03 03 0.11 11 18 cs_neg_noise_th 54 rw ? 14 14 0.11 11 18 cs_low_bl_rst 55 rw ? 14 14 0.11 11 18 cs_filtering 56 rw ? 20 20 0.11 11 19 cs_scan_pos_0 5c rw yes 00 00 ? 11 19 cs_scan_pos_1 [7] 5d rw yes 01 ? 11 19 cs_finger_th_0 66 rw ? 64 64 0.14 11 20 cs_finger_th_1 [7] 67 rw ? 64 0.14 11 20 cs_idac_0 70 rw ? 0a 0a 0.14 11 20 cs_idac_1 [7] 71 rw ? 0a 0.14 11 20 i2c_addr_lock 79 rw ? 01 01 0.11 11 20 device_id 7a r ? 11 21 0.11 11 21 device_status 7b r ? 03 03 0.11 11 21 i2c_addr_dm 7c rw ? 80 80 0.11 11 22 cs_read_button 81 rw ? 81 81 0.12 11 22 cs_read_blm 82 r ? na na 0.12 11 23 cs_read_bll 83 r ? na na 0.12 11 23 cs_read_diffm 84 r ? na na 0.12 11 23 cs_read_diffl 85 r ? na na 0.12 11 23 cs_read_rawm 86 r ? na na 0.12 11 23 cs_read_rawl 87 r ? na na 0.12 11 23 notes 5. these registers are writable only after entering into setup mode. all other registers are available for read and write in nor mal and setup mode. 6. the ack times specified are 1x i2c ack times. 7. these registers are available only in cy8c20121 device.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 11 of 44 cs_read_status 88 r ? na na 0.12 11 24 command_reg a0 w ? 00 00 0.10 11 24 register map (continued) name register address (in hex) access writable only in setup mode [5] factory default values of registers (in hex) i 2 c max ack time in normal mode (ms) [6] i 2 c max ack time in setup mode (ms) [6] page no. 1 button 2 button capsense express commands command [8] description executable mode duration the device is not accessible after ack (in ms) [9] w 00 a0 00 get firmware revision setup/normal 0 w 00 a0 01 store current configuration to nvm setup/normal 120 w 00 a0 02 restore factory co nfiguration setup/normal 120 w 00 a0 03 write nvm por defaults setup/normal 120 w 00 a0 04 read nvm por defaults setup/normal 5 w 00 a0 05 read current configurations (ram) setup/normal 5 w 00 a0 06 reconfigure device (por) setup 5 w 00 a0 07 set normal mode of operation setup/normal 0 w 00 a0 08 set setup mode of operation setup/normal 0 w 00 a0 09 start scan setup/normal 10 w 00 a0 0a stop scan setup/normal 5 w 00 a0 0b get capsense scan status setup/normal 0 notes 8. ?w? indicates the write transfer. the next byte of data represents the 7-bit i 2 c address. 9. the ack times specified are 1x i2c ack times.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 12 of 44 output_status output status register output_status: 00h the output status register represents the actual logical levels on the output pins. output_port output port register output_port: 04h this register is used to write data to dig output port. pins defined as output of co mbinational logic (in op_sel_x register) ca nnot be changed using this register. cs_enable select capsense input register cs_enable: 07h ( writable only in setup mode) 1 button76543210 access: fd r:01 bit name sts[0] 2 button76543210 access: fd r:03 bit name sts[1:0] bit name description 1:0 sts [1:0] used to represent the output status 0 output low 1 output high 1 button76543210 access: fd w:01 bit name dig[0] 2 button76543210 access: fd w:03 bit name dig[1:0] bit name description 1:0 dig [1:0] a bit set in this regist er sets the logic level of the output. 0 logic ?0? 1 logic ?1? 1 button76543210 access: fd rw:01 bit name cs[0] 2 button76543210 access: fd rw:03 bit name cs[1:0]
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 13 of 44 this register is used to enable capsense inputs. this register should be set before setting finger threshold (0x66, 0x67) and idac setting (0x70, 0x71) registers. dig_enable select dig output register gpo_enable: 08h (writable only in setup mode) this register is used to enable dig (dig ital) outputs. if dig output is enabled, the strong drive mode register (11h) should al so be set. if dig output is disabled the drive mode of these pins is high z. set_strong_dm sets strong drive mode for dig outputs. set_strong_dm: 11h (writable only in setup mode) this register sets strong drive mode for dig (digital) outputs. to set strong drive mo de the pin should be enabled as gp output . bit name description 1:0 cs [1:0] these bits are used to enable capsense inputs. 0 disable capsense input 1 enable capsense input 1 button76543210 access: fd rw:01 bit name dig[0] 2 button76543210 access: fd rw:03 bit name dig [1:0] bit name description 1:0 dig [1:0] these bits are used to enable dig outputs. 0 disable dig output 1 enable dig output 1 button76543210 access: fd rw:01 bit name dm [0] 2 button76543210 access: fd rw:03 bit name dm [1:0] bit name description 1:0 dm [1:0] these bits are used to se t the strong drive mode to dig outputs. 0 strong drive mode not set 1 strong drive mode set
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 14 of 44 figure 10. cy8c20111 digital logic diagram figure 11. cy8c20121 digital logic diagram inversion logic dig0 op_sel_0 [0] op_sel_0 [1] logical_opr_input0 [0] op_sel_0 [7] and / or logic selection a b s output_port [0] enb cs0 inversion logic digx op_sel_x [0] op_sel_x [1] and / or logic selection a b s logical_opr_inputx [0] logical_opr_inputx [1] input selection logic op_sel_x [7] and / or logic selection a b s output_port [x] enb enb cs0 cs1
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 15 of 44 op_sel_x logic operation selection registers this register is used to enable logic oper ation on gp outputs. op_sel_0 should be co nfigured to get the logic operation output on dig0 output and op_sel_1 for dig1 output. write to these regist ers during the disable state of respective dig output pins does not have any effect. the input to the logic operation can be selected in logic_oprx re gisters. the selected inputs can be ored or anded. the output of logic operation can also be inverted. logical_opr_inputx selects input for logic operation logical_opr_input0: 1eh logical_opr_ input1: 23h (not available for 1 button) logical_opr_input0 logical_opr_input1 these registers are used to give the input to logic operation block. the inputs can be only capsense input status. op_sel_0: 1ch op_sel_1: 21h (not available for 1 button) 1/2button76543210 access: fd rw: 0 rw: 0 rw: 0 bit name op_en invop operator bit name description 7 op_en this bit enables or disables logic operation. 0 disable logic operation 1 enable logic operation 1 invop this bit enables or disables logic operation output inversion. 0 logic operation output not inverted 1 logic operation output inverted 0 operator this bit selects which operator s hould be used to compute logic operation. 0 logic operator or is used on inputs 1 logic operator and is used on inputs 1 button76543210 access: fd rw:01 bit name csl[0] 2 button76543210 access: fd rw:01 bit name csl [1:0] 2 button76543210 access: fd rw:02 bit name csl [1:0] bit name description 1:0 csl [1:0] these bits selects the input for logic operation block.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 16 of 44 cs_noise_th noise threshold register cs_noise_th: 4eh this register sets the noise threshold value. for individual se nsors, count values above this threshold do not update the basel ine. this count is relative to baseline. this parameter is common for all sensors. the range is 3 to 255 and it should satisfy the equation nt < mi n (finger threshold ? hysteresis ? 5). recommended value is 40% of finger threshold. cs_bl_upd_th baseline update threshold register cs_bl_upd_th: 4fh when the new raw count value is above the current baseline and the difference is below the noise threshold, the difference betw een the current baseline and the raw count is accumulated into a ? bucket.? when the bucket fills, the baseline increments and the b ucket is emptied. this parameter sets the threshold that the bucket mu st reach for the baseline to increment. in other words, lower v alue provides faster baseline update rate and vice ve rsa. this parameter is common for all sensors. the range is 0 to 255. cs_setl_time settling time register cs_setl_time: 50h (writable only in setup mode) the settling time parameter controls the duration of the capacit ance-to-voltage conversion phase. the parameter setting control s a software delay that allows the voltage on the integrating capacitor to stabilize. this parameter is common for all sensors. this register should be se t before setting finger thr eshold (0x66, 0x67) and idac setting (0x70, 0x71) registers. the range is 2 to 255. 1/2 button 7 6 5 4 3 2 1 0 access: fd rw:28 bit name nt[7:0] bit name description 7:0 nt [7:0] these bits are used to set the noise threshold value. 1/2 button76543210 access: fd rw:64 bit name blut[7:0] bit name description 7:0 blut [7:0] these bits set the threshold th at the bucket must reach for baseline to increment. 1/2 button76543210 access: fd rw:a0 bit name stlng_tm[7:0] bit name description 7:0 stlng_tm [7:0] these bits are used to set the settling time value.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 17 of 44 cs_oth_set capsense clock select, sensor auto reset register cs_oth_set: 51h (writable only in setup mode) the registers set the capsense module frequency of oper ation and enables or disables the sensor auto reset. cs_clk bits provides option to select variable clock input for th e capsense block. a sensor design having higher paratactic req uires lower clock for better performance and vice versa. sensor auto reset determines whether the baseline is updated at all times or only w hen the signal difference is below the noise threshold. when set to ?1? (enabled), the baseline is updated cons tantly. this setting limits the maximum time duration of the sensor, but it prevents the sensors from permanently turning on when the raw count sudden ly rises without anything touching the sensor. this sudden rise can be caused by a large power supply voltage fluctuat ion, a high energy rf noise source, or a very quick temperatu re change. when the parameter is set to ?0? (disabled), the baseline is updated only when raw count and baseline difference is bel ow the noise threshold parameter. this parameter may be enabled unle ss there is a demand to keep the sensors in the on state for a long time. this parameter is common for all sensors. cs_hysterisis hysteresis register cs_hysterisis: 52h the hysteresis parameter adds to or subtracts from the finger threshold depending on whether the sensor is currently active or inactive. if the sensor is off, the difference count must overcome the ?finger threshold + hysteres is?. if the s ensor is on, th e difference count must go below the ?finger threshold ? hysteresis?. it is used to add debouncing and ?stickiness? to the finger detection algorithm. this parameter is common for all sensors. possible values are 0 to 255. however, the setting must be lowe r than the finger threshold parameter setting. recommended value for hysteresis is 15 percent of finger threshold. 1/2 button76543210 access: fd rw: 00 rw: 0 bit name cs_clk[1:0] sns_ar bit name description 6:5 cs_clk[1:0] these bits selects the capsense clock. 3 sns_ar this bit is used to enable or disable sensor auto reset. 0 1 disable sensor auto reset enable sensor auto reset cs_clk[1:0] frequency of operation 00 imo 01 imo/2 10 imo/4 11 imo/8 1/2 button76543210 access: fd rw:0a bit name hys[7:0] bit name description 7:0 hys [7:0] these bits are used to set the hysteresis value.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 18 of 44 cs_debounce debounce register. cs_debounce: 53h the debounce parameter adds a debounce counter to the ?sensor acti ve transition?. for the sensor to transition from inactive to active, the consecutive samples of differ ence count value must stay above the ?finger th reshold + hysteresis? for the number specified. this parameter is commo n for all sensors. possible values are 1 to 255. a se tting of ?1? provides no debouncing. cs_neg_noise_th negative noise threshold register cs_neg_noise_th: 54h this parameter adds a negative difference count threshold. if the current raw count is below the baseline and the difference be tween them is greater than this threshold, the baseline is not update d. however, if the current raw count stays in the low state (dif ference greater than the threshold) for the number of samples specified by the low baseline reset parameter, the baseline is reset. thi s parameter is commo n for all sensors. cs_low_bl_rst low baseline reset register cs_low_bl_rst: 55h this parameter works together with the negat ive noise threshold parameter. if the samp le count values are below the baseline mi nus the negative noise threshold for the specified number of samples, the baseline is set to the new raw count value. it essentiall y counts the number of abnormally low samples required to reset the baselin e. it is generally used to correct the finger-on-at-startup c ondition. this parameter is common for all sensors. 1/2 button76543210 access: fd rw:0a bit name db[7:0] bit name description 7:0 db [7:0] these bits are used to set the debounce value. 1/2 button76543210 access: fd rw:0a bit name nnt[7:0] bit name description 7:0 nnt [7:0] these bits are used to set the negative noise value. 1/2 button76543210 access: fd rw:0a bit name lbr[7:0] bit name description 7:0 lbr [7:0] these bits are used to set the low baseline reset value.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 19 of 44 cs_filtering capsense filtering register cs_filtering: 56h this register provides an option for forc ed baseline reset and to enable and configure two different types of software filters. cs_scan_pos_x scan position registers cs_scan_pos_0: 5ch (writable only in setup mode) cs_scan_pos_1: 5dh (not available for 1 button) (writable only in setup mode) this register is used to set the position of the sensors in the switch table for proper scanning sequence because the capsense sensors are scanned in sequence. this register should be set after setting 0x07, 0x50, and 0x51 registers. 1/2 button76543210 access: fd rw: 0 rw: 1 rw: 0 rw: 00 bit name rstbl i2c_ds avg_en avg_order[1:0] bit name description 7 rstbl this bit resets all the baselines and it is auto cleared to ?0?. 0 all baselines are not reset 1 all baselines are reset 5 i2c_ds when this bit is set to ?1? the capsense scan sample is dropped if i 2 c communication was active during scanning. 0 disable the i 2 c drop sample filer 1 enable the i 2 c drop sample filter 4 avg_en this bit enables average filter on raw counts. 0 disable the average filter 1 enable the average filter [1:0] avg_order[1:0] these bits are used to select the number of capsense samples to average: avg_order[1:0] in hex samples to average 00 2 01 4 10 8 11 16 1/2 button76543210 access: fd rw: 0 bit name scan_pstn 2 button76543210 access: fd rw: 1 bit name scan_pstn bit name description 0 scan_pstn this bit sets the scan position.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 20 of 44 cs_finger_th_x finger threshold registers this register sets the finger threshold value for capsense inputs . possible values are 3 to 255. this parameter should be confi gured individually for each capsense inputs. this register should be set after setting 0x07, 0x50, and 0x51 registers. cs_idac_x idac setting registers cs_idac_0: 70h cs_idac_1: 71h (not available in 1 button) the idac register controls the sensitivity of the capsense algorithm. this register is used to tune the capsense input for spec ific design or overlays. decreasing the value of this register increa ses the sensitivity of the capsen se buttons and vice versa. dec reasing the value of idac increases noise and vice versa. possible values are 1 to 255. if the value is set to 0 then the value is reset to default value 10. the recommended value is greater than 4. setting value ? 4 creates excessive amount of noise. this register should be set after setting 0x07, 0x50, and 0x51 registers . i2c_addr_lock i2c address lock registers i2c_addr_lock: 79h this register is used to unlock and lock the i 2 c address register (7ch) access. the device i 2 c address should be modified by writing new address to register 7ch after unlocking the access using this register. write to the 7c register during the locked state do es not have any effect and the new address take effect only after the access is locked. to lock or unlock the i 2 c al bit, the following three byte s must be written to register 79h: unlock i2cal: 3ch a5h 69h lock i2cal: 96h 5ah c3h reading the i2cal bit from register 79h indicates the current access state. cs_finger_th_0: 66h cs_finger_th_1: 67h (not available in 1 button) 1/2 button76543210 access: fd rw: 64 bit name ft[7:0] bit name description [7:0] ft [7:0] these bit set the fi nger threshold for capsense inputs. 1/2 button76543210 access: fd rw: 0a bit name idac[7:0] bit name description [7:0] idac [7:0] these bi t set the idac values. 1/2 button76543210 access: fd wpr: 0 bit name i2cal bit name description 0 i2cal this bit gives the lock/unlock status of i 2 c address. 0 unlocked 1 locked
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 21 of 44 device_id device id register device_id: 7ah this register contains the device and product id. the device and product id corresponds to ?xx? in cy8c201xx. device_status device status register device_status: 7bh this register contains the device status. 1 button76543210 access: fd r: 11 bit name dev_id[7:0] 2 button 7 6 5 4 3 2 1 0 access: fd r: 21 bit name dev_id[7:0] bit name description 7:0 dev_id [7:0] these bits contain the device and product id. part no device/product id cy8c20111 11 cy8c20121 21 1/2 button76543210 access: fd r : 00 r: 0 r : 0 r: 0 r: 0 r: 0 bit name ip_volt[1:0] ires load_fd no_nvm_wr cse dige bit name description 7:6 ip_volt [1:0] supply voltage is automatically detected and these bits are set accordingly. 5 ires when set to ?1?, this bit indica tes that an internal reset occurred. 0 indicates the last system reset was not internal reset 1 indicates the la st system reset was internal reset 4 load_fd this bit indicates whether factory defaults are loaded during power-up. 0 user default configuration is loaded during power-up 1 factory default configurat ion is loaded during power-up 3 no_nvm_wr when set to ?1?, this bit indica tes that the supply voltage applied to the device is too low for a write to nonvolatile memory operation, and no write is performed. this bit must be checked before any store or write por command. 1 cse this bit indicates whether capsense function is enabled or disabled. 0 functionality of capsense block is disabled 1 functionality of capsense block is enabled 0 dige this bit indicates whether gp output function is enabled or disabled. 0 functionality of digital output block is disabled 1 functionality of digital output block is enabled ip_volt[1:0] supply voltage 00 5 01 3.3 10 2.7 11 reserved
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 22 of 44 i2c_addr_dm device i 2 c address and i 2 c pin drive mode register i2c_addr_dm: 7ch this register sets the drive mode of i 2 c pins and i 2 c slave address. to write to this register, register 79h must first be unlocked. the value written to register 7ch is applied only after locking register 79h again. cs_read_button button select register i2c_addr_dm : 81h the scan result of a capsense input (raw count, difference count, and baseline) can be read only for one input at a time using 82h?87h registers. this register is used to select a capsense input to read the raw count, difference count, and baseline. only the pin s defined as capsense inputs in register 07h can be used with this regist er. trying to select other pins not defined as capsense does not have any change. 1 button76543210 access: fd rw: 0 rw: 00 bit name i2cip_en i2c_addr[6:0] bit name description 7 i2cip_en this bit is used to set the i 2 c pins drive mode. 0 internal pull-up enabled 1 internal pull-up disabled 6:0 i2c_addr [6:0] used to set the device i 2 c address. 1 button76543210 access: fd rw: 0 rw: 0 bit name rd_en csbn[0] 2 button76543210 access: fd rw: 0 rw: 00 bit name rd_en csbn[1:0] bit name description 7 rd_en this bit enables the capsense raw data reading. 0 disable capsense scan result reading 1 enable capsense scan result reading 1:0 csbn [1:0] these bits decide which caps ense button scan result are read. when writing to this register, the bitmask must contain only one bit set to ?1?, otherwise the data is discarded. csbn [1:0] capsense button no 01 1 10 2
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 23 of 44 cs_read_blx baseline value msb/lsb registers reading from this register returns the 2-byte curr ent baseline value for the selected capsense input. cs_read_diffx difference count value msb/lsb registers reading from this register returns the 2-byte curr ent difference count for the selected capsense input. cs_read_rawx difference count value msb/lsb registers reading from this register returns the 2-byte curren t raw count value for the selected capsense input. cs_read_blm: 82h cs_read_bll: 83h 1/2 button76543210 access: fd r: 00 bit name bl [7:0] bit name description 7:0 bl [7:0] these bits represent the baseline value. cs_read_diffm: 82h cs_read_diffl: 83h 1/2 button76543210 access: fd r: 00 bit name dif [7:0] bit name description 7:0 dif [7:0] these bits represen t the sensor difference count. cs_read_rawm: 82h cs_read_rawl: 83h 1/2 button76543210 access: fd r: 00 bit name rc [7:0] bit name description 7:0 rc [7:0] these bits represent the raw count value.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 24 of 44 cs_read_status sensor on status register cs_read_status: 88h this register gives the sensor on/off status. a bit ?1? indicates sensor is on and ?0? indicates sensor is off. command_reg command register command_reg: a0h commands are executed by writing the command code to the command register. 1 button76543210 access: fd r: 0 bit name bt_st[0] 2 button76543210 access: fd r: 00 bit name bt_st[1:0] bit name description 1:0 bt_st [1:0] these bits used to represent sensor status. 0 sensor off 1 sensor on 1/2 button76543210 access: fd w: 00 bit name cmnd [7:0] bit name description 7:0 cmnd [7:0] refer to the following table for command register opcodes. command code name description 00h get firmware revision the i 2 c buffer is loaded with the one byte firmware revision value. reading one byte after writing this command returns the firmware revision. the upper nibble of the firmware revision byte is the major revision number and the lower nibble is the minor revision number. 01h store current configuration to nvm the current register settings are saved in nonvolatile memory (flash). this setting is automatically loaded after the next device reset/power-up or if the reconfigure device (06h) command is issued. 02h restore factory configuration replaces the saved user configuration with the factory default configuration. current settings are unaffected by this command. ne w settings are loaded after the next device reset/power-up or if the 06h command is issued. 03h write por defaults sends new power-up defaults to the capsense controller without changing current settings unless the 06h command is issued afterwards. this command is followed by 123 data bytes according to the por default data structure table. the crc is calculated as the xor of the 122 data bytes (00h-79h). if the crc check fails or an incomplete block is sent, the slave responds with an ack and the data is not saved to flash. to define new por defaults: write command 03h write 122 data bytes with new values of regi sters (use the _flash. iic file generated from s/w tool) write one crc byte calculated as xor of previous 122 data bytes
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 25 of 44 04h read por defaults reads the por settings stored in the nonvolatile memory. to read por defaults: write command 04h read 122 data bytes read one crc byte 05h read device configuration (ram) reads the current device configuration. gi ves the user ?flat-address-space? access to all device settings. to read device configuration: write command 05h read 122 data bytes read one crc byte 06h reconfigure device (por) immediately reconfigures the device with ac tual por defaults from flash. has the same effect on the registers as a por. this comm and can only be executed in setup operation mode (command code 08). 07h set normal operation mode sets the device in normal operation mode. in this mode, capsense pin assignments cannot be modified; settling time, idac setti ng, external capacitor, and sensor auto-reset also cannot be modified. 08h set setup operation mode sets the device in setup operation mode. in this mode, capsense pin assignments can be changed along with other parameters. 09h start capsense scanning allows the user to start csa scanning af ter it has been stopped using command 0x0a. note that at por, scanning is enabled and started by default if one or more sensors are enabled. 0ah stop capsense scanning allows the user to stop csa scanning. a system host controller might initiate this command before powering down the device to make sure that during power-down no capsense touches are detected. when csa scanning is stopped by the user and the device is still in the valid v cc operating range, the followi ng behavior is supported: any change to configuration can still be done (as long as v cc is in operating range). command code 0x06 overrides the status of stop/scan by enabling and starting csa scanning if one or more sensors are enabled. capsense read-back values return 0x00. 0bh returns capsense scanning status the i 2 c buffer is loaded with the one-byte csa scanning status value. after writing the value 0bh to the a0h register, reading one byte returns the csa scanning status. it returns the lvd_stop_scan and stop_scan bits. lvd_stop_scan is bit 3 - set when csa is stopped because v cc is outside the valid operating range. stop_scan is bit 2 - set wh en csa is stopped by the user by writing command 0x0a. command code name description
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 26 of 44 layout guidelines and best practices the recommended maximum overlay thickness is 2 mm. for more deta ils refer to the section ?the integrating capacitor (cint)? in an53490 . table 2. layout guidelines and best practices sl. no. category min max recommendations/remarks 1 button shape ? ? solid round pattern, round with led hole, rectangle with round corners 2 button size 5 mm 15 mm 10 mm 3 button button spacing = button ground clearance ?8 mm 4 button ground clearance 0.5 mm 2 mm button ground clearance = overlay thickness 5 ground flood ? top layer ? ? hatched ground 7 mil trace and 45 mil grid (15% filling) 6 ground flood ? bottom layer ? ? hatched ground 7 mil trace and 70 mil grid (10% filling) 7 trace length from sensor to psoc - buttons ? 200 mm < 100 mm. 8 trace width 0.17 mm 0.20 mm 0.17 mm (7 mil) 9 trace routing ? ? traces should be routed on the non sensor side. if any non capsense trace crosses capsense trace, ensure that intersection is orthogonal. 10 via position for the sensors ? ? via should be placed near the edge of the button/slider to reduce trace length thereby increasing sensitivity. 11 via hole size for sensor traces ? ? 10 mil 12 no. of via on sensor trace 1 2 1 13 capsense series resistor placement ? 10mm place capsense series resistors close to psoc for noise suppression.capsense resistors have highest priority place them first. 14 distance between any capsense trace to ground flood 10 mil 20 mil 20 mil 15 device placement ? ? mount the device on the layer opposite to sensor. the capsense trace length between the device and sensors should be minimum 16 placement of components in 2 layer pcb ? ? top layer-sensor pads and bottom layer-psoc, other components and traces. 17 placement of components in 4 layer pcb ? ? top layer-sensor pads, second layer ? capsense traces, third layer-hatched ground, bottom layer- psoc, other components and non capsense traces 18 overlay material ? ? should to be non conductive material. glass, abs plastic, formica 19 overlay adhesives ? ? adhesive should be non conductive and dielectrically homogenous. 467mp and 468mp a dhesives made by 3m are recommended. 20 led back lighting ? ? cut a hole in the sensor pad and use rear mountable leds. refer example pcb layout design with two capsense buttons and two leds on page 28 . 21 board thickness ? ? standard board thickness for capsense fr4 based designs is 1.6 mm.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 27 of 44 figure 12. button shapes figure 13. button layout design x: button to ground clearance y: button to button clearance figure 14. recommended via-hole placement ? ?
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 28 of 44 example pcb layout design with two capsense buttons and two leds figure 15. top layer figure 16. bottom layer ? ?
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 29 of 44 operating voltages for details on i2c 1x ack time, refer table on page 10 and table on page 11 . i2c 4x ack time is approximately four times the values mentioned in these tables. capsense constraints parameter min typ max units notes parasitic capacitance (c p ) of the capsense sensor ? ? 30 pf supply voltage variation (v dd )?? 5%
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 30 of 44 absolute maximum ratings parameter description min typ max unit notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c (0 c to 50 c). extended duration storage temperatures above 65 c degrade reliability t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tri-state v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any gpio pin ?25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd lu latch up current ? ? 200 ma operating temperature parameter description min typ max unit notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 31 of 44 electrical specifications dc electrical specifications dc chip level specifications dc gpio specifications ta b l e 4 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, 3.10 v to 3.6 v ?40 c < ? t a < ? 85 c. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. ta b l e 5 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 v to 2.90 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 2.7 v at 25 c and are for design guidance only. dc por and lvd specifications table 3. dc chip level specifications parameter description min typ max unit notes v dd supply voltage 2.40 ? 5.25 v i dd supply current ? 1.5 2.5 ma conditions are v dd = 3.10 v, t a = 25 c table 4. 5-v and 3.3-v dc gpio specifications parameter description min typ max unit notes v oh1 high output voltage v dd ? 0.2 ? ? v i oh < 10 a/pin, v dd > 3.10 v v oh2 high output voltage v dd ? 0.9 ? ? v i oh = 1 ma/pin, v dd ? 3.10 v v ol low output voltage ? ? 0.75 v i ol = 20 ma/pin, v dd > 3.10 v, maximum of 40 ma sink current i oh high output current 0.01 ? 1 ma v dd ? 3.1 v i ol1 low output current on port 0 pins ? ? 10 ma v dd ? 3.1 v, maximum of 40 ma sink current c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent. temp = 25 c. table 5. 2.7-v dc gpio specifications parameter description min typ max unit notes v oh1 high output voltage v dd ? 0.2 ? ? v i oh ? 10 a/pin v oh2 high output voltage v dd ? 0.5 ? ? v i oh = 0.2 ma/pin v ol low output voltage ? ? 0.75 v i ol = 10 ma/pin, maximum of 20 ma sink current i oh high output current 0.01 ? 0.2 ma v dd ? 2.9 v i ol1 low output current on port 0 pins ? ? 10 ma v dd ? 2.9 v, maximum of 20 ma sink current c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent. temp = 25 c. table 6. dc por and lvd specifications parameter description min typ max unit notes v ppor0 v ppor1 v dd value for ppor trip v dd = 2.7 v v dd = 3.3 v, 5 v ? ? 2.36 2.60 2.40 2.65 v v v dd must be greater than or equal to 2.5 v during startup or reset from watchdog.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 32 of 44 dc flash write specifications ta b l e 7 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, 3.10 v to 3.6 v and ?40 c < t a < 85 c or 2.4 v to 2.90 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are fo r design guidance only. flash endurance and retention specificat ions are valid only within the range: 25 c20 c during the flash writ e operation. it is at the user?s own risk to operate out of t his temperature range. if flash writing is done out of this temper ature range, the endurance and data retention reduces. dc i 2 c specifications this table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c < t a < 85 c, 3.10 v to 3.6 v and ?40 c < t a < 85 c or 2.4 v to 2.90 v and ?40 c < t a < 85 c, respectively. typical parameters apply to 5 v, 3.3 v, or 2.7 v at 25 c. these are for design guidance only. table 7. dc flash write specifications symbol description min typ max units notes v ddiwrite supply voltage for flash write operations [10] 2.7 ? ? v i ddp supply current for flash write operations ? 5 25 ma flash enpb flash endurance 50,000 ? ? ? erase/write cycles flash dr flash data retention 10 ? ? years table 8. dc i 2 c specifications symbol [11] description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 2.4 v ?? v dd ? 3.6 v ? ? 0.25 v dd v 4.75 v ? v dd ? 5.25 v v ihi2c input high level 0.7 v dd ? ? v 2.4 v ? v dd ? 5.25 v v olp low output voltage ? ? 0.4 v i ol = 5 ma/pin, maximum of 10 ma device sink current 2.4 ?? v dd ?? 2.9 v and 3.1 ?? v dd ?? 3.6 v. c i2c capacitive load on i 2 c pins 0.5 1.7 5 pf package and pin dependent. temp = 25 c. r pu pull-up resistor 4 5.6 8 k ? note 10. commands involving flash writes (0x01, 0x02, 0x03) and fl ash read (0x04) must be executed only within the same v cc voltage range detected at por (power on, or command 0x06) and above 2.7 v. 11. all gpio meet the dc gpio v il and v ih specifications found in the dc gpio specifications sections. the i 2 c gpio pins also meet the above specs .
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 33 of 44 ac electrical specifications ac chip-level specifications ac gpio specifications capsense electrical characteristics max (v) typ (v) min (v) conditions for supply voltage result 3.6 3.3 3.1 < 2.9 the device aut omatically reconfigures itself to work in 2.7 v mode of operation. > 2.9 or < 3.10 this range is not recommended for capsense usage. 2.90 2.7 2.45 < 2.45 v the scanning for capsense parameters shuts down until the voltage returns to over 2.45 v. > 3.10 the device automatically reconfig ures itself to work in 3.3 v mode of operation. < 2.4 v the device goes into reset. 5.25 5.0 4.75 < 4.73 v the scanning for capsen se parameters shuts down until the voltage returns to over 4.73 v. table 9. 5-v and 3.3-v ac chip-level specifications parameter description min typ max units notes f 32k1 internal low-speed oscillator (ilo) frequency 15 32 64 khz calculations during sleep operations are done based on ilo frequency. t xrst external reset pulse width 10 ? ? s t powerup time from end of por to cpu executing code ? 150 ? ms sr power_up power supply slew rate ? ? 250 v/ms table 10. 2.7-v ac chip-level specifications parameter description min typ max units notes f 32k1 internal low-speed oscillator (ilo) frequency 8 32 96 khz calculations during sleep operations are done based on ilo frequency. t xrst external reset pulse width 10 ? ? s t powerup time from end of por to cpu executing code ? 600 ? ms sr power_up power supply slew rate ? ? 250 v/ms table 11. 5-v and 3.3-v ac gpio specifications parameter description min max unit notes t rise rise time, strong mode, cload = 50 pf 15 80 ns v dd = 3.10 v to 3.6 v and 4.75 v to 5.25 v, 10% to 90% t fall fall time, strong mode, cload = 50 pf 10 50 ns v dd = 3.10 v to 3.6 v and 4.75 v to 5.25 v, 10% to 90%
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 34 of 44 ac i 2 c specifications figure 17. definition of timing for fast/standard mode on the i 2 c bus table 12. 2.7-v ac gpio specifications parameter description min max unit notes t rise rise time, strong mode, cload = 50 pf 15 100 ns v dd = 2.4 v to 2.90 v, 10% to 90% t fall fall time, strong mode, cload = 50 pf 10 70 ns v dd = 2.4 v to 2.90 v, 10% to 90% table 13. ac i 2 c specifications parameter description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 kbps fast mode not supported for v dd < 3.0 v t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0?0.6?s t lowi2c low period of the scl clock 4.7 ? 1.3 ? s t highi2c high period of the scl clock 4.0 ? 0.6 ? s t sustai2c setup time for a repeated start condition 4.7?0.6?s t hddati2c data hold time 0 ? 0 ? s t sudati2c data setup time 250 ? 100 ? ns t sustoi2c setup time for stop condition 4.0 ? 0.6 ? s t bufi2c bus free time between a stop and start condition 4.7?1.3?s t spi2c pulse width of spikes suppressed by the input filter ??050ns i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 35 of 44 appendix examples of frequently used i 2 c commands si. no. requirement i 2 c commands [12] comments 1 enter into setup mode w 00 a0 08 2 enter into normal mode w 00 a0 07 3 load factory defaults to ram registers w 00 a0 02 4 do a software reset w 00 a0 08 w 00 a0 06 ; enter into setup mode ; do software reset 5 save current configuration to flash w 00 a0 01 6 load factory defaults to ram registers and save as user config- uration w 00 a0 08 w 00 a0 02 w 00 a0 01 w 00 a0 06 ; enter into setup mode ; load factory defaults to sram ; save the configuration to flas h. wait for time specified in capsense express commands on page 11 . ; do software reset 7 disable combinational logic output to dig0 w 00 1c 00 8 disable combinational logic output to dig1 w 00 21 00 9 clearing (logic 0) the both dig0 and dig1 outputs w 00 04 00 combinational logic output on dig0 and dig1 should be disabled before dong this operation (sl# 7 and 8) 10 setting (logic 1) the dig0 and clearing (logic 0) the dig1 outputs w 00 04 01 11 clearing (logic 0) the dig0 and setting (logic 1) the dig1 outputs w 00 04 02 12 setting (logic 1) the both dig0 and dig1 outputs w 00 04 03 13 change capsense clock to imo/2 w 00 a0 08 w 00 51 20 w 00 a0 07 ; enter into setup mode ; capsense clock is set as imo/2 ; enter into normal mode 14 change value of idac0 to ?x?h w 00 70 x ?x? represents new value of idac register 15 change value of idac1 to ?y?h w 00 71 y ?y? represents new value of idac register 16 change value of idac0 and idac1 to ?x?h and ?y?h w 00 70 x y ?x? and ?y? represents new value of idac register 17 change the value ft0 to ?x?h w 00 66 x ?x? represents new value of ft register 18 change the value ft1 to ?y?h w 00 67 y ?y? represents new value of ft register 19 change the value ft0 and ft1 to ?x?h and ?y?h w 00 66 x y ?x? and ?y? represents new value of ft registers 20 change noise threshold to ?x?h w 00 4e x 21 read capsense button cs0 scan results w 00 81 81 w 00 82 r 00 rd rd rd rd rd rd ; select capsense button for reading scan result ; set the read point to 82h ; consecutive 6 reads gets baseline, difference count and raw count (all two byte each) 22 read capsense button status register w 00 88 r 00 rd ; set the read pointer to 88 ; reading a byte gets status capsense inputs note 12. the ?w? indicates the write transfer and the next byte of data represents the 7-bit i2c address. the i2c address is assumed to be ?0? in the above examples. similarly ?r? indicates the read transfer followed by 7-bit address and data byte read operations.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 36 of 44 ordering information note for die sales information, contact a local cypress sales office or field applications engineer (fae). ordering code definitions thermal impedances solder reflow specifications ordering code package diagram package type operating temperature capsense blocks capsense inputs digital outputs xres pin CY8C20111-SX1I 51-85066 8-pin soic industrial yes 1 1 no CY8C20111-SX1It 51-85066 8-pin soic (tape and reel) industrial yes 1 1 no cy8c20121-sx1i 51-85066 8-pin soic industrial yes 2 2 no cy8c20121-sx1it 51-85066 8-pin soic (tape and reel) industrial yes 2 2 no table 14. thermal impedance by package package typical ? ja [13] 8-pin soic 127.22 c/w table 15. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 8-pin soic 260 ? c 30 seconds x = blank or t blank = tube; t = tape and reel temperature range: i = industrial 1 = 8-pin device pb-free package type: s = 8-pin soic part number: xx = 11 or 21 family code technology code: c = cmos marketing code: 8 = controllers company id: cy = cypress i c201xx-sx cy 8 1 x note 13. t j = t a + power x ? ja.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 37 of 44 package diagram figure 18. 8-pin soic (150 mils) s08.15/sz08.15 package outline, 51-85066 51-85066 *e
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 38 of 44 acronyms ta b l e 1 6 lists the acronyms that are used in this document. document conventions units of measure ta b l e 1 7 lists the units of measures. numeric conventions hexadecimal numbers are represented with all letters in uppercas e with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pr efix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 16. acronyms used in this datasheet acronym description acronym description ac alternating current lvd low voltage detect cmos complementary metal oxide semiconductor pcb printed circuit board crc cyclic redundancy check pga programmable gain amplifier csa capsense successive approxi mation por power on reset csd capsense sigma delta ppor precision power on reset dc direct current psoc ? programmable system-on-chip eeprom electrically erasable programmable read-only memory pwm pulse width modulator emc electromagnetic compatibility qfn quad flat no leads gpio general-purpose i/o slimo slow internal main oscillator i/o input/output spitm serial peripheral interface idac current dac sram static random access memory ilo internal low speed oscillator srom supervisory read only memory imo internal main oscillator ssop shrink small-outline package lcd liquid crystal display u sb universal serial bus ldo low dropout regulator wdt watchdog timer led light-emitting diode wlcsp wafer level chip scale package lsb least-significant bit xres external reset table 17. units of measure symbol unit of measure symbol unit of measure ? c degree celsius mm millimeter kbps kilo bits per second ms millisecond khz kilohertz na nanoampere k ? kilohm ns nanosecond lsb least significant bit % percent a microampere pf picofarad s microsecond v volt ma milliampere w watt
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 39 of 44 glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs , multi-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. application programming interface (api) a series of software routines that comprise an interf ace between a computer application and lower level services and functions (for example, user m odules and libraries). apis serve as building blo cks for programmers that create software applications. asynchronous a signal whose data is acknowledged or ac ted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the posi tive temperature coefficien t of vt with the negative temperature coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or info rmation processing system measured in hertz. 2. the width of the spectral region over which an amplifie r (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field ) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perform one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for i/o operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and ca rrying similar data. typically represented using vector notation; for example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed freq uency and duty cycle. a clo ck is sometimes used to synchronize different logic blocks. comparator an electronic circuit that pr oduces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high level language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in which the frequency is cont rolled by a piezoelectric crystal. typically a piezoelectric crys tal is less sensitive to ambient temperature than other circuit components.
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 40 of 44 cyclic redundancy check (crc) a calculation used to detect errors in data communi cations, typically performed using a linear feedback shift register. similar calculations may be used for a va riety of other purposes such as data compression. data bus a bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allows you to analyze the operation of the system under development. a debugger usually allows the developer to step through t he firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counte r, timer, serial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog-to-digital (adc) converter performs the reverse operation. duty cycle the relationship of a cl ock period high time to its low time, expressed as a percent. emulator duplicates (provides an emulat ion of) the functions of o ne system with a different syst em, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc devic e. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volat ile technology that provides you the programmability and data storage of eproms, plus in-system erasability. non-vola tile means that the data is retained when power is off. flash block the smallest amount of flas h rom space that may be pr ogrammed at one time and the smallest amount of flash space that may be protected. a flash block holds 64 bytes. frequency the number of cycles or events per unit of time, for a periodic function. gain the ratio of output current, voltage, or power to input current, voltage, or power, re spectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductor s (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the origi nal system was created in the early 1980s as a battery control inte rface, but it was later used as a si mple internal bus system for building control electronics. i2c uses only two bi-directional pi ns, clock and data, both running at +5 v and pulled high with resistors. the bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ice the in-circuit emulator t hat allows you to test the project in a hard ware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a de vice that introduces data into or extracts data from a system. interrupt a suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a wa y that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exist with its own priority an d individual isr code block. each isr code block ends with the reti instruction, returning the device to the point in the program where it left normal program execution. jitter 1. a misplacement of the ti ming of a transition from its ideal position. a typical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more si gnal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. glossary (continued)
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 41 of 44 low-voltage detect (lvd) a circuit that senses v dd and provides an interr upt to the system when v dd falls lower than a selected threshold. m8c an 8-bit harvard-architecture microprocessor. the mi croprocessor coordinates all activity inside a psoc by interfacing to the flash, sram, and register space. master device a device that controls the timing for data exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device . microcontroller an integrated ci rcuit chip that is designed prim arily for control systems and produc ts. in addition to a cpu, a microcontroller typically includes memory, timing circuits, a nd i/o circuitry. the reason for this is to permit the realization of a controller with a mini mal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or more characteristic s of any entity such as voltage, current, or data. oscillator a circuit that may be crystal contro lled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a bi nary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation between t he logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer gen erated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the vo ltage is lower than a pre-set level. this is a type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programm able system-on-chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a func tion of the appl ied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specif ic capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware re set and software reset. rom an acronym for read only memory. a data-storage devi ce from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. glossary (continued)
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 42 of 44 settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to anothe r. shift register a memory storage device that sequentially shifts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external in terface. the controlling dev ice is called the master device. sram an acronym for static random access memory. a memo ry device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly altered or unt il power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or ac ted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. tri-state a function whose output can ad opt three states: 0, 1, and z (high-imp edance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-transmitter tr anslates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardware/fi rmware peripheral functions that take ca re of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the regist er map. the registers in this bank are more likely to be modified during normal program execution and not just during initialization. registers in bank 1 ar e most likely to be modified only during the initialization p hase of the program. v dd a name for a power net meaning "voltage drain." the mo st positive power supply sig nal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of tim e. glossary (continued)
cy8c20111, cy8c20121 document number: 001-53516 rev. *h page 43 of 44 document history page document title: cy8c20111/cy8c20121, capsense ? express? ? one button and two button capacitive controllers document number: 001-53516 rev. ecn no. orig. of change submission date description of change ** 2709248 slan / pyrs see ecn new data sheet. *a 2821828 sshh / fsu 12/4/2009 added contents . updated registers (updated register map , added output_status ). updated absolute maximum ratings (added f32k u, t powerup parameters and their details). updated electrical specifications (updated dc electrical specifications (updated dc flash write specifications (updated note 10 ))). *b 2868929 slan 01/28/2010 changed stat us from preliminary to final. updated package diagram (spec 51-85066 (changed revision from *c to *d)). *c 2892629 njf 03/15/2010 updated absolute maximum ratings (added t baketemp and t baketime parameters and their details). added thermal impedances . added solder reflow specifications . *d 3043236 arvm 09/30/10 updated absolute maximum ratings (removed f32ku, t powerup parameters and their details). updated electrical specifications (updated ac electrical specifications (added ac chip-level specifications )). *e 3087790 njf 11/16/10 updated electrical specifications ((updated dc electrical specifications (updated dc gpio specifications (removed sub-section ?2.7-v dc spec for i 2 c line with 1.8 v external pull-up?), added dc i2c specifications )), updated ac electrical specifications (updated ac i 2 c specifications (updated figure 17 (no specific changes were made to i2c timing diagram. updated for clearer understanding.)))). updated solder reflow specifications . added acronyms and units of measure . added glossary . updated in new template. *f 3148656 arvm 01/20/11 updated layout guidelines and best practices (updated ta b l e 2 (removed ?overlay thickness-buttons? category), added the following statement after table 2 ? ?the recommended maximum overlay thickness is 2 mm. for more details refer to the section ?the integrating capacitor (cint)? in an53490 .?). updated capsense constraints (removed the parameter ?overlay thickness?). updated solder reflow specifications (updated table 15 ). *g 3287607 arvm 06/20/11 post to external web. *h 3631370 vair / slan 05/31/2012 updated typical circuits (updated figure 6 (added note 3 and referred the same note in figure 6 )). updated in new template.
document number: 001-53516 rev. *h revised may 31, 2012 page 44 of 44 all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c20111, cy8c20121 ? cypress semiconductor corporation, 2009-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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